In this paper， a high‑performance power amplifier operating in S‑band was designed by the 0.35 μm gate length and 60 V high voltage GaN HEMT process developed by Nanjing Electronic Devices Institute and the AlGaN/GaN scalable large signal model simulation guidance. The power amplifier was designed by a single GaN die with a total gate width of 36.4 mm using a hybrid integrated internal matching scheme. The drain voltage was 60 V and the frequency band was 2.7‑3.5 GHz. The test results show that the saturated output power of the power amplifier can reach up to 350 W， the power additional efficiency can reach up to 61% and the power gain is greater than 14.5 dB in the operating frequency band under the condition of pulse test with ambient temperature of 300 K， pulse width of 250 μs and duty cycle of 15%， which fully demonstrates the characteristics of GaN devices such as high working voltage， high power density and wide operating bandwidth.

When the diamond surface is treated by hydrogen plasma， an accumulation layer of two-dimensional hole gas （2DHG） will be formed with a density of about 10¹³ cm^-2. Therefore， field-effect transistors fabricated using hydrogen-terminated diamond （H-diamond） have become the focus of research. This paper is based on the outstanding physical properties of diamond and mainly discusses two formation mechanisms of H-diamond 2DHG， methods to stabilize 2DHG and improve device performance based on the depletion mode H-diamond MOSFET device structure， and three approaches to realize enhancement mode H-diamond MOSFET. Furthermore， the current research status， the challenges faced and prospects for future development are summarized.

The fabrication of traveling wave tube （TWT） slow-wave structures typically employs computer-numerically-controlled precision machinery. As the operating frequency increases， the requirement for the precision of the characteristic dimensions of the slow-wave structure reaches the micron to nanometer scale， which presents significant challenges in machining and involves long cycles and high costs， and thus limiting the rapid development of the technology. Silicon-based MEMS processing technology offers excellent three-dimensional morphological molding， high precision control and good batch-to-batch consistency. This paper addresses the design requirements for a dual-slot deep-folded waveguide slow-wave structure for THz TWT power source， and developed a three-dimensional integrated process manufacturing technology based on silicon substrate. A method combining photoresist masking with dielectric masking is employed， and the balance between the etching and passivation processes during deep reactive ion etching （DRIE） is carefully optimized. The process is then completed with electroplating gold and gold-gold bonding. Therefore， high-performance silicon-based terahertz slow-wave structures have been successfully manufactured at 150-mm wafer level with a working frequency of 0.65 THz and the insertion loss as low as 1.6 dB/mm， which helps establish technical foundations for technological breakthrough and application development of terahertz TWTs.

Wafer bonding technology has been widely applied in power semiconductor optoelectronic devices， electronic power devices， high-power solid-state lasers， MEMS， and optical integration fields. Wafer bonding technology can be divided into two major categories based on whether the bonding is achieved through an intermediate layer. Among them， direct wafer bonding technology belongs to the category of bonded without an intermediate layer. The key aspect of this technology lies in the selection of the wafer pretreatment process. This article summarizes the characteristics of different direct wafer bonding pretreatment technologies in the wet and dry directions， including the technical principles and key points of solution cleaning， steam cleaning， rapid atom beam bombing， plasma surface activation， and ultraviolet light activation. Furthermore， the future innovation and improvement of direct wafer bonding pretreatment technology are discussed.

To meet the demand for low loss power combiners in the development of terahertz solid‑state power amplifiers， a 4‑way radial waveguide power combiner was developed at 200‑240 GHz with gap waveguide technology. The passive tested return loss is better than -15 dB， with a passive combining efficiency of 88.7%， which shows the low‑loss characteristics of the gap waveguide at terahertz band. Based on the power amplifier module packaged with two GaN MMICs， further active power combining is carried out. A peak output power of 311 mW is achieved at 220 GHz， and the average power combining efficiency of 81% is got cross over the frequency band of 200‑240 GHz.

In order to solve the design requirements of miniaturization and lightweighting of the system， an integrated SiP transceiver module that supports BeiDou RNSS and RDSS was designed in this paper. The working frequency band supports the three frequency points of BeiDou B3/L/S. The SiP module adopted an integrated ceramic packaging architecture， and multiple RF passive devices and digital analog chips were integrated through heterogeneous and heterogeneous integration. The isolation shielding was realized by using metal cavity shielding and multi‑row cross metal through hole structure， and the passive devices such as filter， multiplexer， balun and transmission structure were simulated and designed. The final size is 24.0 mm×24.0 mm×4.3 mm， with good performance. The article introduces the working principle， key technologies， and final implementation form of the SiP transceiver module， and the design results meet the relevant application requirements of positioning and navigation terminals.

Hydrogen-terminated diamond microwave power devices with low on-resistance and high current density had been fabricated by using a self-aligned gate technique. A low ohmic contact resistance of 0.73 Ω·mm is achieved for the hydrogen terminated diamond by employing a high work-function contact metal Au. Attributing to the low source and drain series resistances and low damage deposition process of AlO gate dielectric by atomic layer deposition （ALD）， the diamond microwave device realizes a low on-resistance of 4 Ω·mm， a high current density of 1.01 A/mm， a high transconductance of 213 mS/mm， as well as a high maximum oscillation frequency of 58 GHz. The power output characteristics at frequency of 2 GHz and 10 GHz in continuous wave mode have been researched and it is found that the high output power density of 1.56 W/mm and 1.12 W/mm are obtained， respectively， showing the potential of the self-alignment technique for fabricating high-current and high-power diamond microwave devices.

In the post-Moore era， the development of semiconductor technology relies mainly on two paths： More Moore and more than Moore. Using new processing and new material， more Moore is pushing the line width to 3 nm and even the order of angstroms. On the other hand， more than Moore uses heterogeneous three dimensional micro-nano integration to meet the needs of the next generation of high speed， low power， and high performance electronics. Heterogeneous integration takes advantage of properties of different materials to optimize system performance. RF integration technology promotes the breakthrough of high frequency microelectronics from planer 2D to 3D， and becomes an important way for the development of high frequency microelectronics in the post-Moore era. 3D RF heterogeneous integration technology has all the benefits of Si‑based fabrications， such as processing accuracy， good batch consistency， and wafer level stacking. Heterogeneous integration technology leads to the miniaturization of passive devices， chipization of RF module and miniaturization of RF systems. This paper introduces the development trend of RF three-dimensional micro-nano technology， and gives the development and application cases of RF MEMS devices， RF MEMS modules and three-dimensional RF micro-systems at home and abroad by using RF three-dimensional micro-nano integration technology.

Fabrication of 35 nm enhancement-mode InP high electron mobility transistors on 101.6 mm InP wafer was achieved. By utilizing InAs composite channel structure， the product of the room temperature two dimensional electron gas mobility and sheet density reached 4.2×10/（V·s）. Using PtTiPtAu buried gate technology， the peak transconductance of the typical device reached 2 900 mS/mm， the cutoff frequency reached 460 GHz， the maximum oscillation frequency reached 720 GHz. Meanwhile， a 340 GHz low-noise amplifier was prepared， with a small signal gain of 22-27 dB and a noise figure below 8 dB were achieved within the frequency range of 310-350 GHz. The technology platforms of 340 GHz InP low-noise amplifier were established， which paved the way for the developments of terahertz low-noise monolithic microwave integrated circuit.

We first summarize the important reform measures of NSFC in 2022. Secondly， we analyze the application， acceptance and funding status of projects in the field of “semiconductor science and information devices” in this year， as well as the distribution of supporting organizations of the most widely involved projects of general program and scientist fund， and carry out statistical analysis on the attributes of four types of scientific problems of the proposals. Then， we analyze and discuss the reform of the evaluation mechanism of “responsibility， credibility， contribution” （RCC） in the “semiconductor science and information devices” field. Finally， suggestions are given to project applicants and experts respectively， and the priority development direction of “semiconductor science and information devices” is prospected.

Terahertz phased array systems， serving as the cornerstone of future communication and radar technologies， hold immense potential in applications such as 6G communication， satellite communication， and ultra‑low‑latency systems. This paper provided an overview of the primary architectures of terahertz phased array systems， encompassing schemes like intermediate frequency （IF） phase shifting， local oscillator （LO） phase shifting， baseband phase shifting， and radio frequency （RF） phase shifting. It further analyzed their respective advantages， disadvantages， and technical challenges in diverse application scenarios. Special attention was paid to the research progress of terahertz phased array systems based on complementary metal oxide semiconductor （CMOS） technology and terahertz phased array transceivers， covering design breakthroughs from the W‑band to beyond 0.5 THz. These emerging technologies offer novel design perspectives for high‑frequency phased array systems and are poised to play a pivotal role in future ultra‑high‑speed communication and low‑latency applications.

In order to improve the function stability of low voltage differential linear voltage regulator in radiation environment， an anti-radiation layout reinforcement technique for deep sub-micro LDO was proposed in this paper. The anti-irradiation capability of the circuit had been improved by using the large-head strip gate and P+ protection ring and other structures， combined with process reinforcement and layout design technology. The test results show that the LDO circuit designed in this paper has good power supply rejection ratio， gain and fast transient response. The irradiation experiments show that the total dose of ionizing radiation is more than 300 krad（Si）， and the threshold for single event latch-up （SEL） is greater than 75 MeV·cm²/mg， the error rate for single event upset （SEU） is less than 1×10^-10 error/（bit·day）. So， the deep sub-micron LDO circuit meets irradiation resistance requirements.

In recent years， the terahertz frequency band has garnered extensive attention as an alternative frequency band for the next-generation 6G communication technology， and terahertz has thus emerged as a research focus. Terahertz integrated circuits （chips） are crucial for facilitating the rapid development of various terahertz application systems. With the continuous enhancement of characteristic frequency and maximum oscillation frequency（f_T/f_max） of silicon-based processes， it becomes feasible to achieve fully integrated silicon-based terahertz transmitters in the terahertz frequency band using silicon-based processes. This article briefly reviews significant research advancements in terahertz transmitter chip technologies based on silicon-based processes， including 150 GHz direct up conversion transmitter chips， 220 GHz sliding intermediate-frequency superheterodyne transmitter chips， and D-band direct modulation transmitter chips. Experimental results have verified the advantages of the terahertz frequency band in high-speed communication applications. Silicon-based terahertz transceiver integrated circuits are expected to be the key technology for breaking through the requirements of high data rates in 6G systems.

With the promising application prospects of terahertz technology in fields such as detection， imaging， and communication， silicon-based terahertz systems have attracted widespread attention due to their advantages of low cost， small size， high integration， and easy implementation of large-scale arrays. Silicon-based terahertz power amplifiers （PAs） are important modules in silicon-based terahertz systems， which determine the energy consumption， maximum radiation distance， and signal quality of the system. In recent years， the design of silicon-based terahertz PAs has made significant progress. This article will summarize the research status and technological development trend of silicon-based terahertz PAs from four aspects： The application scenarios of terahertz technology and the position of PAs in terahertz transceiver， the key technical indicators and design difficulties of silicon-based terahertz PAs， the progress of terahertz PAs based on CMOS/CMOS SOI processes， and the progress of terahertz PAs based on SiGe processes.

The capability of enhanced β-Ga₂O₃ VDMOS devices against SEGR was investigated in this article， utilizing TCAD simulations to examine the impacts of various gate dielectric materials. Devices with high-k gate dielectrics （Al₂O₃ and HfO₂） demonstrate effective immunity against a heavy ion strike with a linear energy transfer of 98 MeV·cm²/mg under the bias conditions of a drain-source voltage of 200 V and a gate-source voltage of -10 V. In contrast， devices with SiO₂ gate dielectrics experience single event gate rupture （SEGR）. Remarkably， HfO₂ exhibite a substantial decline in both drain-source current and gate-source current by 92% and 94%， respectively. HfO₂ gate sample also reduce the peak electric field from 1.5×10⁷ V/cm to 2×10⁵ V/cm， effectively avoiding SEGR. We determine that SEGR arises from substantial hole accumulation in the channel， triggered by exceeding the critical threshold in the gate dielectric's electric field. High-k gate dielectrics decrease the impact generation rate in the device's sensitive regions， further suppress the continuous creation of electron-hole pairs and minimize the probability of hole accumulation.

Based on terahertz monolithic integration technology， a 560 GHz subharmonic mixer was designed. The three-dimensional electromagnetic model of the diode was established for full-wave simulation. Combined with the SPICE parameter model of the diode， a complete diode model including parasitic parameters and intrinsic parameters was obtained. The circuit was simulated and optimized based on the half-subdivision and half-global design method， which is flexible and the size of the circuit is small. The whole circuit is designed on a 3 μm thick GaAs membrane， effectively suppresses the transmission of higher-order modes and reduces the transmission loss. The stress support is provided by laying a large area of beam⁃lead to ensure the stability of the circuit. The experimental results show that when the local oscillator drive power is 3 mW， the conversion loss of the mixer is less than 11 dB within 520-600 GHz.

Large-scale phased array systems are one of the core and key factors for the flexible application of terahertz wireless transmission technology. This article introduces the development bottleneck of large-scale terahertz phased array technology and the research progress. The paper focused on introducing the tile-type splicing solution， which interconnected 16 CMOS chips through gold wire bonding to form the largest-scale terahertz phased array transmitter with 64 elements （8×8）. Through the balanced direct current power supply network and the "forward radiation + back heat dissipation" architecture， good direct current supply and heat treatment was achieved to ensure working performance of array. The peak effective isotropic radiation power （EIRP） can reach 35 dBm， the local oscillator signal leakage suppression and the image frequency signal suppression are both greater than 35 dB， and the horizontal and vertical directions achieve ±60° beam coverage. This article also introduces the world's longest distance 52 m terahertz phased array real-time wireless communication link， and the system transmission rate can reach 1.6 Gbit/s.

Two GaN Schottky barrier diodes （SBDs） on SiC were fabricated with different doping concentration and thickness of low doped GaN epitaxial layer. The results show that the SBD prepared with epitaxial layer thickness of 80 nm and doping concentration of 8×10¹⁷ cm^-3，which has a cut-off frequency up to 1.2 THz. Based on this SBD， a balanced frequency tripler terahertz monolithic integrated circuit （TMIC） was fabricated. At room temperature， the output power of this frequency tripler reaches 10 mW to 25 mW in the range of 305 GHz to 330 GHz with max efficiency of 3.3% in continuous wave mode.

To fulfill the requirements for low noise and wide bandwidth in IEEE 802.11ax applications， a wideband low noise amplifier （LNA） operating at 5.3‑7.4 GHz was designed. By utilizing a passive transformer for noise cancellation， the noise figure is improved by 0.27 dB compared to non‑cancellation designs， without increasing power consumption. The device incorporated a switched capacitor array for a tunable inter‑stage network， providing 700 MHz sub‑band and 2.1 GHz overall tuning bandwidths. Additionally， a wideband output matching network was designed based on the constant‑Q circle strategy. Fabricated in 22 nm CMOS process， the chip testing results demonstrate a 3 dB bandwidth of 2.1 GHz and a peak gain of 26.5 dB. Furthermore， the noise figure remains below 2.53 dB， and the gain exceeds 23 dB across the entire 5.3 to 7.4 GHz spectrum， with a power consumption of 43 mW.

The stress evolution and control of defect density of terahertz GaN Schottky barrier diode （SBD） epitaxy grown on 101.6 mm （4-inch） semi-insulating SiC substrate were studied by metal organic chemical vapor deposition （MOCVD）. A stress modulation scheme based on AlGaN transition layer was proposed， achieving stress well in control for GaN SBD epitaxy. Simultaneously， a pulse-doping process at a lower temperature was introduced into n+-GaN layer， which remarkably reduces density of defects and improves crystalline quality of GaN SBD epitaxy. The as-grown 101.6 mm GaN SBD epitaxy possesses a wafer bow/warp of -12/18 μm， fullwidth at halfmaximum （FWHM） of （002）/（102） peaks of 148/239 arcsec， sheet resistance of 9.2 Ω/□ with nonuniformity in wafer of 1.1%. Finally， a GaN SBD device is fabricated based on the own epitaxy， showing a cut-off frequency up to 1.12 THz.

Terahertz （THz） metasurfaces exhibit remarkable light-field manipulation capabilities due to their ability to capture incident photons at sub-wavelength scales and generate strong confined field-enhancing effects at resonance frequencies. Photonic bound states in the continuum （BIC） are non-radiative eigenstates located in the radiative continuum， with two outstanding properties of infinitely high Q factor and momentum spatial polarization vortex， which bring new opportunities for customization of high-Q resonance and enhanced light field manipulation in terahertz metasurface. This paper reviews the historical development of optical BIC， summarizes the physical properties and formation mechanism of different types of BIC in periodic optical systems， and discusses the generation and evolution of BIC from topological perspectives. In addition， the review focuses on the emerging applications of BIC-driven metasurfaces in THz photonics， and concludes with a discussion of the challenges and prospects in this field.

The output voltage of conventional CMOS voltage references varies greatly with the supply voltage， and in order to meet the accuracy requirements， the supply voltage range of conventional CMOS voltage references is limited. In this paper， a CMOS voltage reference with wide supply voltage was proposed. The output voltage accuracy of the voltage reference was improved by reducing the variation of the bias current. In addition， operational amplifier circuits and bipolar transistors were not used in the voltage reference circuit， which reduced the chip area. The proposed voltage reference has been fabricated using a 0.18 μm CMOS process and the die size is 0.026 mm. The simulated and measured results show that the output voltage of the voltage reference varies about 0.176%/V as the supply voltage changes from 1.8 V to 5 V. When the temperature varies from -25℃ to 125℃， the temperature coefficient of the output voltage is about 82.78×10 V/℃. The power supply rejection ratio of the output voltage is -60 dB when the frequency of the power supply noise is 1 kHz.

In this paper， a tripler working at 330-400 GHz was developed using the GaAs Schottky diode technology. In the triple frequency circuit， a passive reverse parallel balanced structure was achieved by setting the arrangement direction of diode cores perpendicular to the signal transmission direction. This structure can suppress even harmonics， enhance odd harmonics and improve the frequency doubling efficiency. To reduce packaging errors， the monolithic integration technology was used to integrate the Schottky diode and peripheral circuits on a 25 µm thick GaAs substrate， creating a chip. The chip was then packaged into the shielding cavity to form a waveguide-suspended microstrip line structure for a small circuit loss. The test results show that within the 330-400 GHz range， the output power of the tripler is greater than 5.5 dBm at the input power of 22 dBm， and the peak output power is better than 7 dBm.

A low-phase-noise four-stage differential phase-locked loop （PLL） based on SMIC 0.18 μm CMOS process was designed. By adding additional charge and discharge paths and optimizing the charge pump structure with a unity gain amplifier， non-ideal factors such as clock feedthrough and charge sharing in the PLL circuit were effectively reduced， meanwhile the feedback loop with retiming timing structure was adopted to eliminate the accumulation of noise in the circuit. The test results demonstrate that at an input reference frequency of 40 MHz， the output center frequency of the PLL can be locked at 960 MHz within 5 μs and the phase noise is -125 dBc/Hz @ 1 MHz. It can solve the issue of traditional PLL structures which are unable to meet the high-precision time-to-digital conversion （TDC） circuit requirements due to poor noise suppression performance.

Based on the 40 V high voltage complementary bipolar junction transistor （BJT） compatible with junction field effect transistor （JFET） technology， a high voltage precision low input bias current JFET amplifier was designed. The overall structure and working principle of the amplifier were described. Inside the circuit， JFET input devices were used to reduce the input bias current and improve the bandwidth. The input offset voltage was reduced by adjusting the resistance. The four-core transconductance structure was used to optimize the intermediate stage to improve the swing rate of the op amp. The complementary push-pull output structure was used in the output stage to prevent crossover distortion and improve the power driving ability. The bias circuit used JFET as a constant current source to ensure stable power supply under different working voltages. The chip test results show that， under ±5‑±13 V power supply conditions， the circuit has the input offset voltage ≤80 μV； the input bias current ≤1.5 pA； the large signal voltage gain ≥107 dB； the gain bandwidth product ≥25 MHz； the slew rate ≥50 V/μs.

Carbon is the element exhibiting very high content in nature， and its numerous allotropes have significantly contributed to the ongoing advancement of society and technology. Especially in the semiconductor field， diamond， graphene and carbon nanotubes， with their ultra-high carrier mobility and unique energy band structure， have great prospects for applications in high frequency， high power and even power electronics. This paper reviews the research progress of carbon-based materials （diamond， graphene and carbon nanotubes） in radio frequency （RF） electronic devices， including material preparation， characterization， RF electronic device processes and recent achievements. Finally， the current challenges of carbon-based materials in RF applications are discussed，along with the prospects for future development of carbon-based RF devices.

A 3-bit MEMS digital attenuator with wafer-level packaging was implemented, which had a working frequency range of DC to 15 GHz, an attenuation range of 0 to 35 dB and a step size of 5 dB. The attenuator was fabricated using MEMS process and employed coplanar waveguide （CPW） structure for signal transmission. Six direct contact MEMS switches were symmetrically placed to realize different attenuation states. Each switch had three contacts, and the resistive network adopted a T-type structure. The entire attenuator was packaged at the wafer level. Test results show that eight attenuation states are achieved within the frequency range of DC-15 GHz, with the insertion loss less than 1.7 dB, the return loss less than -15 dB, the attenuation flatness less than ±5%,and the power consumption is almost negligible. The chip size is 2.7 mm×2.7 mm×0.8 mm.

In order to improve the reliability and security of FPGA， a low power system monitor circuit was designed in this paper. By monitoring the internal working voltage， temperature and external voltage of FPGA， the working mode or frequency of FPGA can be adjusted in time. In the circuit of the system monitor， a self-balancing integral amplifier was used to realize the sampling and amplification of temperature sensing signals. Single-terminal mode and differential mode were supported for voltage sensing signals. A 1.5-bit cyclic ADC was used to quantify the analog signals. In addition， a reference circuit was designed by switching capacitor， which provides a reference voltage with low temperature coefficient for ADC， and it has the characteristics of low power consumption. The test results show that the monitoring temperature ranges from -55℃ to 125℃， and the maximum deviation is -1.5℃. The maximum deviation of single terminal voltage monitoring is -1.3%， and that of differential voltage monitoring is 0.1%. The monitoring circuit of the system has good temperature characteristics and frequency characteristics. In the temperature range of -55‑125°C， the deviation of ADC output results is within 2%. In the frequency range of 0.2-5.0 MHz， the influence of clock frequency on ADC can be ignored. At the maximum operating frequency of 5 MHz， the maximum power consumption is only 2.32 mW.

In order to improve the maximum controllable current of the large‑area integrated gate commutated thyristor （IGCT）， 4.5 kV large‑area IGCT with a diameter of 91 mm was studied. In response to the failure phenomenon frequently occurred at the cathode units far from the gate contact of IGCT during the research and development process， a simulation structural model of the large‑area IGCT chip was established. The corresponding turn‑off stress was applied to the device， and the failure phenomenon was simulated and analyzed. The results show that due to a turn‑off signal delay at the cathode unit far from the gate contact， the inhomogeneous current distribution between the inner and outer rings occurs during the device commutation， and this effect is intensified when dynamic avalanche effect occurs. Until the avalanche‑induced current filament is generated， the cathode unit in the outer ring will be re‑triggered， leading to device destruction due to local over‑heating. The use of radial carrier lifetime control can suppress the inhomogeneous current distribution effect caused by signal delay in large‑area IGCT， and improve the maximum turn‑off current capability of the device.

Due to the high operating voltage， wide dynamic range， and strong nonlinear characteristics of GaN HEMT devices， along with continuously rising chip design specifications， a high-precision nonlinear model has become the foundation for successful designs. Furthermore， a quantitative analysis of the sources of nonlinear products is crucial for process improvement and design optimization. Therefore， based on the traditional model architecture， a voltage-controlled scaling function for key model parameters was introduced， achieving higher model accuracy over a wide dynamic range. At the same time， a model architecture with multiple intrinsic ports and adjustable nonlinear patterns was proposed， allowing for quantitative analysis of the sources of nonlinear products.

Field‑effect transistors （FETs） constructed based on aligned carbon nanotube （ACNT） materials have emerged as strong candidates for high‑performance and low‑power FETs in the post‑Moore era， owing to their exceptional carrier mobility， potential for dimensional scaling， compatibility with complementary‑metal‑oxide‑semiconductor （CMOS） technology， and the feasibility of wafer‑scale fabrication. This paper reviews the fabrication processes of carbon nanotube FETs， analyzing and evaluating their advantages and limitations from the perspectives of material preparation， transistor architecture， contact engineering， and dielectric engineering. Current process challenges for carbon‑based FETs are summarized， and strategies suitable for ultra‑large‑scale integrated circuits are discussed. Finally， the future development of carbon nanotube transistor fabrication processes is envisioned.

The microstructure morphology of nano silver slurry before and after sintering was analyzed， and the effects of different sintering temperatures， sintering times， and heating rates on the shear strength of nano silver slurry sintered samples were studied. The effects of two different connecting materials， Au80Sn20 and nano silver slurry， on the heat dissipation performance of GaN chips were compared and analyzed. The results indicate that after sintering the GaN chip into the shell through nano silver slurry， there is a clear interdiffusion layer between the silver layer and the gold layer， achieving excellent interconnection between the chip and the shell. Under sintering conditions of 200℃， 90 min， and 5℃/min， the shear strength of the sample can reach 47.2 MPa. The temperature distribution of the chips assembled with nano silver slurry and Au80Sn20 is basically the same， but the heat dissipation performance of nano silver slurry is better than that of Au80Sn20. After undergoing temperature shock， vibration， temperature cycling， and RF aging tests， the thermal resistance of the chip sintered with nano silver paste did not fluctuate significantly， and the shear performance slightly improved.

A design of new structure of slow wave time-delay chip is shown in this paper. It was developed and tested based on 0.15 μm E/D pHEMT process. Slow wave time-delay， single pole double throw switch and digital driver were integrated. The electromagnetic simulation software was used to optimize the length， space and corner structure of the slow-wave structure， which could optimize the time-delay performance and improve integration； a series-parallel hybrid structure with high isolation and low insertion loss was adopted in the single pole double throw switch； a highly integration pHEMT process was used in the digital driver， which could achieve two stable output phase oppositional voltages. The on-chip test results show that the insertion loss is less than 8.5 dB， the time delay is up to 850 ps， the is less than 1.7， the amplitude error is less than ±0.8 dB at 5-14 GHz and the static power consumption is 1 mA@-5 V. The size of the chip is 6.7mm×5.0 mm.

This article addresses the issue of high-temperature packaging and interconnection for current high-temperature power chips. It reviews the research status and trends of novel lead-free high-temperature solder materials， nano-sintering technology， transient liquid phase bonding， and transient liquid phase sintering （TLPS） connections both domestically and internationally. The advantages and disadvantages of various technologies are analyzed. Analysis has found that the application of nanoparticle materials and TLPS connection technology to high-temperature device packaging has significant advantages in low-temperature connection and high-temperature service. However， during the sintering process of nanoparticle materials， organic matter is difficult to volatilize， Cu nanoparticles are easily oxidized， and Ag nanoparticle joints have problems such as electromigration. During the TLPS sintering process， due to the volatilization of organic binders and the volume shrinkage of particles， holes are produced in the joint， leading to a reduction in the electrical conductivity and thermal conductivity of the joint. These problems can be solved by adding alloy elements， improving the process， and compounding the solder， which will promote the development of the high-temperature electronic packaging industry.

Based on traditional trench gate gallium nitride field-effect transistors， an AlGaN layer was introduced to reduce the on-state resistance of the device using two dimensional electron gas. Discussions were conducted on the thickness and doping concentration of the drift layer， and device optimization was performed using TCAD software. The final optimized drift layer thickness was determined to be 6 μm， with a doping concentration of 5×10¹⁶ cm^-3. The device achieves a low on-state resistance （R_on） of 0.47 mΩ·cm²， a high breakdown voltage （V_BR）of 2 880 V， and a figure of merit （FOM） of 17.6 GW·cm^-2. The results demonstrate the advantages of the trench gate vertical GaN FET for high-voltage， high-current applications.

In order to satisfy the high electrostatic discharge （ESD） protection requirements of AlGaN/GaN HEMT devices， a novel ESD protection structure for GaN HEMT with doped trench was proposed. The current discharge capability of HEMT was enhanced when facing ESD events due to the created trench. Furthermore， the trench was created between the gate and drain， the impact on the gate control was minimized， thereby ensuring the stability of gate. The simulated results show that compared to the conventional HEMT structure， the discharge current of the proposed structure increases by 32.7%. Furthermore， when the distance between the trench and the gate exceeds 0.3 μm， the trench has no discernable effect on the threshold voltage.

Based on 0.15 μm GaAs pHEMT technology， a 6-bit high-precision numerical control phase shifter monolithic microwave integrated circuit with working frequency of 18 to 40 GHz was proposed. An improved phase shifter circuit with series and parallel capacitors was utilized in the 5.625°，11.25° and 22.5° phase bits， which could improve phase shifting accuracy by adding series inductors into the circuit. The magnetically coupled all-pass network was used in the 45° and 90° phase bit. In the 180° phase bit， a modified phase shifter based on the series and shunt resonators was employed to extend the bandwidth and achieve higher phase shifting precision. The fabricated chip occupied the size of 2.8 mm×1.4 mm. The measurement results demonstrate that the root mean square value of phase errors is less than 2.3°， and the RMS value of amplitude error is less than 0.7 dB within the operating frequency of 18 to 40 GHz. The insertion loss is less than 13.5 dB among all phase states. The input and output are better than 1.7 and 1.9 among all phase states， respectively.

Threshold voltage and gate leakage are crucial parameters for assessing the performance of GaN HEMT devices with an enhanced Si-based p-GaN gate structure. The variation of thermal stress and electrical stress will facilitate the electron tunneling effect near the gate of the device， and facilitate the interaction between hot electrons and device defects to form an interface state， thereby resulting in the increase of gate leakage and threshold voltage drift. The long-term operation will cause the deterioration of gate characteristics and impede the large-scale engineering application of GaN power electronic devices. In this paper， an enhanced p-GaN GaN HEMT device was fabricated based on the 101.6 mm （4 inch） GaN device technology platform. The two-layer source field plate and source grounding hole structure were investigated， and the influence of this structure on the gate leakage and threshold voltage of the device was explored. The threshold voltage of the device at low temperature （-50℃） varies by 0.4 V compared with that at high temperature （155℃）. After a 200 V drain stress test， the threshold voltage of the device varies by 0.24 V， the threshold voltage shifts by 0.2 V when the drain voltage varies， and the variation is lower than that of device without this structure. Furthermore， when the gate voltage attains a value of 5 V， the gate leakage current of the fabricated 400 μm device amounts to 1.4 μA， and undergoes a variation of approximately 0.1 μA subsequent to the thermal stress and electrical stress tests. The test outcomes manifest that the developed enhanced p-GaN grid structure GaN HEMT is competent to operate securely in intricate environments.

By optimizing the metal structures and evaporation-annealing conditions， low contact resistivity and high stability p-GaN ohmic contact was achieved， and the diffusion behavior of electrode metals during the alloying process was analyzed. The test results demonstrate that the optimized ohmic contact to p-type GaN exhibits a contact resistance of 11.9 Ω·mm and a specific contact resistivity of 3.9×10^-5 Ω·cm². Furthermore， the contact characteristics do not degrade in high-temperature environments below 250℃. Based on these findings， an enhancement-mode p-channel GaN device was fabricated utilizing low-damage gate recess etching and dual-layer gate dielectric deposition techniques， yielding a threshold voltage of -1.2 V （V_GS=V_DS，I_DS=10 μA/mm）， a maximum drain current of -5.6 mA/mm， and an on-resistance of 665 Ω·mm （V_GS=-8 V，V_DS=-2 V）. This outstanding p-type ohmic contact technique establishes a crucial foundation for the development of high-performance GaN p-channel devices and contributes to the advancement of miniaturization， intelligence， and high-speed capabilities in GaN CMOS technology.