25 April 2025, Volume 45 Issue 2

    

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  Research Progress on Ga₂O₃ Radio Frequency Devices

  YU Xinxin, SHEN Rui, QIAO Bing, LI Zhonghui, YE Jiandong, KONG Yuechan, CHEN Tangsheng

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502001

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  Gallium oxide （Ga₂O₃） is an ultra-wide bandgap semiconductor material with excellent performance， which not only has large critical breakdown electrical field and high saturation velocity， but also has extremely high Baliga's and Johnson's figure of merits， which makes it of important application prospects in the field of power and radio frequency （RF） devices. This paper focuses on Ga₂O₃ RF devices. The advantages and challenges of Ga₂O₃ in the field of RF devices were introduced. And then the progress made in bulk doped channels， AlGaO/Ga₂O₃ modulation doped heterojunctions， as well as hetero-integrating with high thermal conductivity substrates in recent years were reviewed and their research results were discussed. Finally， the development prospects of Ga₂O₃ RF devices in the future were expected.
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  Study on Depletion Mode GaN Nonvolatile Memory

  SHAO Guojian, CHEN Tao, ZHOU Shutong, LI Xin

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502002

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  The depletion mode GaN nonvolatile memory based on the SiO₂/SiN/AlGaN/GaN structure was investigated in this paper. The SiN dielectric layer and SiO₂ layer were set as the charging storage layer and isolation layer， respectively. By applying a positive voltage to the gate， the memory enters the program mode， and electrons are introduced into the charging storage layer. Conversely， when a negative voltage is applied to the gate， the memory enters the erase mode， and the charging storage layer is cleared， returning the memory to its initial state. After reliability verifications， such as 10⁴ cycles of program/erase and 10⁴ seconds of data retention， the memory still maintains sufficient window capacity.
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  Design of Fast Detection Circuit for Voltage and Current Overshoot of Active Gate Drive of Silicon Carbide MOSFETs

  WANG Junbo¹, ZHANG Yin¹, TANG Qi¹, WANG Zhenglei², CHEN Yukai², LIU Ping³

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502003

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  Silicon carbide metal-oxide-semiconductor field-effect transistors （SiC MOSFETs） are widely used due to their advantages of high operating frequency and high temperature resistance. However， high electrical stresses on the switch， voltage-current overshoots and switching oscillations in SiC MOSFETs drive circuits significantly reduce the reliability of the converter. In order to improve the reliability of the system， a fast detection circuit for the overshoot of voltage and current driven by the active gate of SiC MOSFETs was proposed in this paper. Firstly， the turn-on and turn-off processes of SiC MOSFETs were analyzed， and a fast detection circuit was designed for the voltage and current overshoot states in the rising and falling stages of the drain current. Then， in order to suppress voltage and current spikes， a control circuit was designed to dynamically regulate the gate current. Finally， according to the schematic diagram， the device selection scheme was determined and the test platform was built to analyze the working performance of the selected device and its own hardware delay. Experimental results show that the proposed design scheme can quickly detect the voltage and current overshoot states， and effectively suppress the voltage and current spikes.
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  Design and Manufacture of 4H‑SiC High Temperature Driving Circuit

  TIAN Yuan, HUANG Runhua, NI Chaohui, LIU Tao, ZHANG Guobin, YANG Yong, BAI Song

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502004

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  In order to solve the problem that the performance of SiC MOSFET was limited by silicon‑based driving circuit at high temperature， a driving circuit based on 4H‑SiC material was designed and manufactured in this paper to improve the overall high temperature resistance of the circuit. The performance of the driving circuit was tested at room temperature （25℃） and high temperature （300℃）. At room temperature， the rising edge delay and falling edge delay of the driving circuit under no‑load condition are 2.496 μs and 1.32 μs respectively， and they are 1.61 μs and 0.816 μs respectively at 300℃. Under the conditions of an output power of 100 W， an output voltage of 56 V， and a bus voltage of 320 V， the driving circuit was subjected to load testing. At room temperature， the peak charging and discharging current are 129 mA and 120 mA respectively， and they are 264 mA and 221 mA respectively at 300℃. The test results show that the driving circuit can work normally when the ambient temperature is 300℃， and with the ambient temperature rising from 25℃ to 300℃， the driving ability and response speed of the driving circuit are gradually improved.
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  Design of a Watt‑level Solid‑state Amplifiers with Power Combining Technology Up to 0.17 THz

  ZHAO Bo, CHENG Haifeng, HU Zunyue, ZHU Xiang, DU Jiayu, GONG Bing

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502005

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  In view of the current engineering application requirements of the high power solid-state amplifier at terahertz （THz） band， the research of 0.17 THz watt-level solid-state power amplifier （PA） with power combining technology was carried out in this paper. Based on 3‑dB waveguide bridge structure and THz GaN power amplifier chips， a two-chip packaged PA module was designed and manufactured with a typical output power of 410 mW. A G-band 4-way waveguide combiner was realized using the E-plane T-junction structure. The tested passive combining efficiency is 76%， covering the frequency range of 155 to 200 GHz. By combining 4 packaged PA modules， the output power of more than 0.82 W is obtained in the frequency range of 165 to 175 GHz， with a typical output power of 1.3 W at 175 GHz， and the active combining efficiency is 72%.
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  Research Progress on Terahertz Voltage‑controlled Oscillators

  CHEN Shangxuan, LU Chengjian, CHEN Zhuoheng, CHENG Binbin, CHENG Xu

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502006

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  The rapid development of terahertz （THz） technology in recent years has driven the design and realization of THz oscillators and voltage-controlled oscillators （VCOs）. With the advancement of semiconductor technologies such as CMOS， SiGe， and GaAs， the implementation of high-frequency oscillators and VCOs with high integration， low power consumption， and low phase noise has become feasible. This review discusses the key technologies of THz oscillators and their latest research progress， focusing on the design methods of different types of THz oscillators， particularly research on output power improvement and tuning techniques. Through a comprehensive analysis of existing literature， this paper aims to provide researchers with a panoramic understanding of the field of silicon-based THz oscillators and offer references and guidance for future research.
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  Research on the Ultra⁃wideband Interconnection Technology for 3D⁃SiP Module

  LYU Jiaran, KAN Yao, LIU Shijie, XU Mengyuan, TANG Juntan, CHENG Haifeng

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502007

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  In response to the evolving trend of active phased array antenna front-ends towards low profile， ultra-wideband， and high integration， research has emerged focusing on TR modules based on three-dimensional system-in-package （3D-SiP） technology. This paper was centered on a 3D-SiP TR module implemented using high temperature co-fired ceramic （HTCC） technology and ball grid array （BGA） stacking for ultra-wideband interconnect structures. Ultra-wideband simulation studies were conducted on three basic structures， upon which the internal interconnect structure for the 3D-SiP TR module was subsequently realized. Furthermore， physical prototypes were developed and tested on the high-density 3D assemblies within the frequency range of 2 GHz to 18 GHz. It is indicated by the test results that， within the 2-18 GHz frequency band， the 3D-SiP TR module exhibits a reflection coefficient of less than -10 dB and an insertion loss of less than 3.8 dB.
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  A High‑tuning‑linearity Low‑phase‑noise Quadrature VCO

  ZHANG Jingjing, SHI Chunqi, CHEN Guangsheng, HUANG Leilei, ZHANG Runxi

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502008

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  A quadrature voltage-controlled oscillator （QVCO） designed for integrated sensing and communication was presented in this paper， and the relationships among phase noise， tuning linearity， and tuning range were analyzed. The tuning range and linearity of the QVCO were optimized using a nonlinear correction method with digital temperature compensation， while the impact of external noise on the noise of QVCO was also considered. Fabricated with a 55 nm CMOS process， the QVCO achieves a tuning range from 22.748 to 28.302 GHz （21.76%）， with a minimum tuning linearity of 18.2%. At a 1 MHz offset from the carrier frequency， the measured phase noise ranges from -114.40 to -110.49 dBc/Hz， and the corresponding figure of merit （FOM） lies between -194.08 and -192.06 dBc/Hz. And the standardized phase noise spans from -201.41 to -199.53 dBc/Hz over the entire tuning range.
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  A Ka‑band Power Amplifier Based on Coupled‑line Power Combining

  SUN Han, YANG Xiaozheng, HE Jin

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502009

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  In this paper， a Ka‑band power amplifier （PA） was designed based on a 55‑nm RF CMOS process for 5G millimeter‑wave communications. Using asymmetric couplers， a novel power combining network （PCN） was proposed to be applicable to technology in which metal traces are of different thickness. With such easy‑to‑implement and low‑loss PCN， PA's output power was significantly improved. In addition， PA's gate bias could be changed by the proposed adaptive biasing circuit according to PA's input power thus mitigating the gain compression effect and enhancing linearity. The simulated results show that the PA achieves a small signal gain -3 dB bandwidth of 25.0‑28.8 GHz. With a 1.8 V supply， the PA realizes a 20.1 dB peak small signal gain， a 19.3 dBm saturate output power and a 17.6 dBm 1 dB compression output power. The PA also realizes a maximum power added efficiency of 17.1% and a core area of 0.18 mm².
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  A High Isolation Dual‑frequency MIMO Antenna for 5G Applications

  Zhu DUAN, MASUM BILLAH, BAI Rubing

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502010

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  A high isolation dual-frequency multiple-input multiple-output （MIMO） antenna for 5G was proposed in this paper. The antenna adopted a circular monopole as the antenna element， and the new resonance was generated by etching a C-shaped slot on the circular radiation patch， which realized the dual-frequency characteristics of the antenna. The edge spacing between the antenna elements is only 12 mm （0.14λ_L， λ_L is the free space wavelength at the low frequency resonance point 3.5 GHz）. In order to avoid strong coupling between the antenna elements due to the close distance， the isolation between the antenna elements is effectively improved by introducing T-shaped decoupling branch and etching rectangular slot structure on the metal floor. The final size of the antenna is 58.0 mm×34.0 mm×1.6 mm. The test results show that the working frequency band （|S₁₁|<-10 dB） of the antenna is 2.71-3.92 GHz and 4.45-5.60 GHz， and the relative bandwidth is 36.5% and 22.9%， the isolation between the antenna elements is greater than 26 dB and 28 dB， respectively， and the envelope correlation coefficient is less than 0.004.
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  Design of the Thermoelectric Energy Acquisition Chip with Ultra‑low Input Voltage

  YANG Miao¹, ZHOU Junhao², LIU Xinning²

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502011

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  Based on the 0.18 μm 1P4M BCD process， the design of a power chip with ultra-low input voltage， self-starting and step-up functions is realized， and the external thermoelectric energy is collected and managed. The feedback control circuit and the charging control circuit are combined， and the hysteresis comparator array and cross-coupling multiplexing circuit are adopted to realize the master-slave power switching and output control functions so that it can still work normally when there is no external energy input. The experiment results show that under the low input voltage of 22 mV， the chip can be self-starting. The quiescent current of the chip is only 3.5 μA， with the maximum output voltage of 4.2 V and a maximum output current of 950 μA.
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  A Low‑power Step‑down DC‑DC Converter Design

  SONG Fuheng, CAI Tiantian, WANG Peihao, WANG Ziyang, XIA Xiaojuan

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502012

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  An ultra-low static power consumption synchronous rectifier buck pulse frequency modulation （PFM） mode DC-DC converter was designed. The output voltage startup circuit was utilized to reduce the static power consumption under light load conditions and inductive peak current limiting was added to reduce the output voltage ripple. Based on the 0.5 μm CMOS process for design as well as simulation verification， the test results show that the chip's quiescent current is only 760 nA when the output voltage is 1.8 V. The full-load efficiency is above 90%， and the maximum efficiency can reach 93.12%.
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  Effect of Anode Annealing on the Performance of Co Anode Quasi‑vertical GaN Based Schottky Barrier Diodes

  WU Zhiyong, MA Qun, WANG Liangchen, LI Jinmin, WANG Junxi, LIU Zhiqiang, YI Xiaoyan

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502013

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  In this work， the Cobalt （Co） anode quasi‑vertical GaN Schottky barrier diode （GaN SBD） with different anode finger widths were fabricated on sapphire substrate， and then subjected to anode annealing at 300， 350， 400℃ respectively. The experimental results show that a smaller anode finger width is beneficial for achieving lower specific on‑resistance. After annealing at 300℃， anode interface states decrease and the uniformity of metal‑semiconductor contact increases， the turn‑on voltage and specific on‑resistance of the device decrease by 12.1% and 13.2%， respectively. In addition， the leakage current density at reverse 3 V decreases by nearly an order of magnitude， the breakdown voltage increases from 89 V to 97 V. As the annealing temperature increases， the Schottky characteristics of the device gradually weaken. The comprehensive results indicate that annealing at 300℃ can effectively improve the performance of Co anode GaN SBD.
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  A Vertical Hall‑effect Device with Improved Sensitivity and Its Simulation Model

  WANG Shuangxi, LI Jianqiang, LI Liang, ZHOU Lin, LI Jielin, XU Yue

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502014

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  A sensitivity-improved five-contact vertical Hall-effect device （FCVHD） was fabricated based on a 180 nm BCD process. It employs a low-doped and deep N-type drift region （NDR） as the device's active region and implements P⁺ diffusion isolation between N⁺ contacts on the device surface， which effectively reduces short-circuit effects， thus enhancing the current-related sensitivity （S_IV） of the FCVHD. Additionally， dual PN junction guard rings were designed around the device's active region to more effectively suppress substrate noise and interference. Furthermore， a simplified Verilog-A circuit simulation model was developed for the device， which consists of only nonlinear resistors， nonlinear capacitors， and current-controlled voltage sources， considering non-ideal device effects for high simulation accuracy. Measured results demonstrate that the S_IV of this vertical Hall device reaches 24 V/（A·T）， with a 2.86 times improvement compared to the sensitivity of the standard CMOS N-well device. The model simulation results exhibit good consistency with experimental measurements， with a <3.7% relative error， validating its practicality.
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  Research on New SiGe‑HBT Devices with Pseudo N‑type Buried Layer and Its Application

  LIU Donghua, CHEN Xi, QIAN Wensheng

  RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS. 2025, 45(2): 0. https://doi.org/10.12450/j.gtdzx.202502015

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  A novel germanium silicon heterojunction bipolar transistor （SiGe-HBT） structure was proposed in this article. The deep isolation grooves， N-type buried layers， and collector regions formed by epitaxial growth in traditional SiGe-HBT were eliminated. By using ion implantation technology at the bottom of the shallow isolation to form an N-type pseudo buried layer （PNBL）， the lateral expansion of the collector area has been achieved. This structure includes a longitudinal collecting region located below the intrinsic base region and a transverse collecting region formed by a PNBL at the bottom of the field oxygen. The DC and RF characteristics of the new SiGe-HBT device were tested， and the results showed that the cutoff frequency of the high-speed transistor reached 100 GHz， with a current gain of 270. By increasing the distance between the PNBL and the active region of the collector， the high voltage withstand characteristics of the device were achieved. A power amplifier is designed using high-voltage SiGe-HBT devices with BV_ceo=10 V. At a power supply voltage of 4.5 V and an input power of 0 dBm， the output power of the power amplifier reaches 27.5 dBm， with an efficiency of nearly 50%.