An Optimization Design of GPGPU Microarchitecture for Barrier Synchronization

JIA Shiwei

RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS ›› 2023, Vol. 43 ›› Issue (1) : 70-77.

PDF(901 KB)
PDF(901 KB)
RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS ›› 2023, Vol. 43 ›› Issue (1) : 70-77.
Si Microelectronics

An Optimization Design of GPGPU Microarchitecture for Barrier Synchronization

    {{javascript:window.custom_author_en_index=0;}}
  • {{article.zuoZhe_EN}}
Author information +
History +

HeighLight

{{article.keyPoints_en}}

Abstract

{{article.zhaiyao_en}}

Key words

QR code of this article

Cite this article

EndNote

Ris (Procite)

Bibtex

Download Citations
{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2023, 43(1): 70-77

References

Publishing order | Descend order by publishing year | Descend order by cited within

References

{{article.reference}}

Funding

RIGHTS & PERMISSIONS

{{article.copyrightStatement_en}}
{{article.copyrightLicense_en}}
PDF(901 KB)

Accesses

Citation

Detail
Sections
Recommended
Copyright © RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS, All Rights Reserved.
Powered by Beijing Magtech Co. Ltd,.

/

〈 〉