Effect of Layout and Process on ESD Characteristics of High‑voltage GGNMOS

FU Fan, WAN Fayu, WANG Yu, HONG Genshen

RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS ›› 2024, Vol. 44 ›› Issue (2) : 178-182.

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RESEARCH & PROGRESS OF SOLID STATE ELECTRONICS ›› 2024, Vol. 44 ›› Issue (2) : 178-182. DOI: 10.12450/j.gtdzx.202402014
Device & Material & Technology

Effect of Layout and Process on ESD Characteristics of High‑voltage GGNMOS

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{{article.zuoZheEn_L}}. {{article.title_en}}[J]. {{journal.qiKanMingCheng_EN}}, 2024, 44(2): 178-182 https://doi.org/10.12450/j.gtdzx.202402014

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